Optical computing has shown immense application prospects in the post-Moore era. However, as a crucial component of logic computing, the digital multiplier can only be realized on a small scale in optics, restrained by the limited functionalities and inevitable loss of optical nonlinearity. In this paper, we propose a time-space multiplexed architecture to realize large-scale photonic-electronic digital multiplication. We experimentally demonstrate an 8×2-bit photonic-electronic digital multiplier, and the multiplication with a 32-bit number is further executed at 25 Mbit/s to demonstrate its extensibility and functionality. Moreover, the proposed architecture has the potential for on-chip implementation, and a feasible integration scheme is provided. We believe the time-space multiplexed photonic-electronic digital multiplier will open up a promising avenue for large-scale photonic digital computing.

With the advancement of deep learning and neural networks, the computational demands for applications in wearable devices have grown exponentially. However, wearable devices also have strict requirements for long battery life, low power consumption, and compact size. In this work, we propose a scalable optoelectronic computing system based on an integrated optical convolution acceleration core. This system enables high-precision computation at the speed of light, achieving 7-bit accuracy while maintaining extremely low power consumption. It also demonstrates peak throughput of 3.2 TOPS (tera operations per second) in parallel processing. We have successfully demonstrated image convolution and the typical application of an interactive first-person perspective gesture recognition application based on depth information. The system achieves a comparable recognition accuracy to traditional electronic computation in all blind tests.

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